1. Field of the Invention
This invention relates generally to a Class-D line driver, and, and in particular to an improved Class-D line driver for Asymmetric Digital Subscriber Line (ADSL) applications.
2. Background of the Invention
Recently, broadband network applications are increasingly being implemented on digital subscriber lines (DSL), especially on asymmetric digital subscriber lines (ADSL). ADSL has proven to be a preferred technology, since ADSL delivers a good bit rate at low cost to the resident.
ADSL is a new technology that allows more data to be sent over existing copper telephone lines that are used for plain old telephone service (POTS). Unlike cable modem technology, ADSL does not require any costly improvements to the telephone lines. ADSL supports data rates of approximately 1.5 megabits per second (Mbps) to 9 Mbps when receiving data (known as the downstream rate), and supports data rates of approximately 16 kilobits per second (Kbps) to 640 Kbps when sending data (known as the upstream rate). ADSL requires a modified ADSL modem, but the modifications are minor.
ADSL line coding is DMT (Discrete Multi-Tone). DMT line coding consists of 256 carriers that can individually transmit and receive data. This type of line coding is resistant to channel noise, and individual carriers in the noisy part of the channel can be turned off. However, DMT line code has a high Peak-to-Average Ratio (PAR). The large PAR is due to the fact that the addition of 256 carriers at random creates a random signal with an even larger distribution. The high PAR requires line drivers that can supply large peaks of power on demand. The average PAR for a DMT signal is approximately 5.4.
Almost all current line drivers that are presently used for ADSL are linear line drivers with AB output stages. These types of line drivers have very low power efficiencies. The best prior art linear line driver for ADSL transmission from a Central Office (CO) has approximately a 10% power efficiency, which means it dissipates approximately one watt of power for every 100 milliwatts delivered to the load.
The other major requirements for ADSL line drivers are low noise and low distortion. Since the received signal at a remote office at a long distance from the CO is weak, and the transmitted power is large, any distortion on the part of the line driver will corrupt the received signal.
A typical pulse-width-modulation (xe2x80x9cPWMxe2x80x9d) type line driver (i.e., the Class-D line driver) includes a comparator circuit coupled to the gates (or bases) of a pair of switching transistors that are coupled in series across a D. C. power source. The transistors are disposed in a conventional push-pull configuration. Reverse current bypass or recovery diodes are also coupled in series across the D. C. power source, and the junction of the diodes is coupled to the junction of the paired transistors. A low-pass filter is coupled to the junction of the paired transistors.
The comparator creates a rectangle-wave PWM signal from a modulating input signal and a triangle-wave carrier signal. The PWM signal is applied to the gates of the switching transistors, causing the transistors to be alternately switched on and off in accordance with the duration of the PWM pulses. The resulting demodulated signal passes through the low-pass filter and is output to a load.
Although highly power efficient compared to linear drivers, conventional Class-D line drivers are subject to output distortion. Class-D line drivers generate output distortion due to a mismatch in the output transistors.
An additional cause of output distortion in conventional Class-D line drivers is pulse amplitude error (i.e., crossover distortion) over the analog cycle of the modulating input signal. Class-D line drivers include a pair of switching transistors and recovery diodes. When an analog input signal passes from a positive to negative half cycle, effective output drive is transferred from one transistor and recovery diode to the other transistor and recovery diode. This transition creates a crossover distortion component in the output waveform resulting from recovery diode over-swings and forward voltage drops of the xe2x80x9conxe2x80x9d transistor. Finally, Class-D line driver output is also subject to high-frequency ripple distortion created by the frequency of the carrier signal creating PWM waveforms.
FIG. 1 is a circuit diagram of a conventional Class-D line driver. A typical distortion level for the output of a conventional open loop Class-D line driver is 0.1%, which is not adequate for an ADSL modem application. The signal 102 is an input to the PWM block 104, which provides an output signal received as an input signal to the gates of transistors 106 and 108. The output from the drains of transistors 106 and 108 is connected through line 110 to load capacitance 112 and load resistance 114. The source of transistor 108 is connected to an appropriate bias voltage VDD. Load resistance 114, load capacitance 112, and the source of transistor 106 are connected to ground (GND).
FIG. 2 is a circuit diagram of a closed loop Class-D line driver. The signal 102 is an input to subtractor 202, which outputs a signal to a loop filter 204 that may optionally include a PWM. The output of loop filter 204 provides an output signal received as an input signal to the gates of transistors 106 and 108. The output signal from the drains of transistors 106 and 108 is connected through line 110 to load capacitance 112 and load resistance 114. The output signal of transistors 106 and 108 is also a feedback signal subtracted by subtractor 202. The source of transistor 108 is connected to an appropriate bias voltage VDD. Load resistance 114, load capacitance 112, and the source of transistor 106 are connected to ground (GND).
This circuit architecture has the benefit of canceling errors at the line driver output by the feedback loop. This type of circuit architecture can achieve xe2x88x9280 Decibels (dB) total harmonic distortion (THD) at low frequencies less than 20 kilohertz (KHz). This type of circuit architecture can achieve xe2x88x9260 dB at higher frequencies, but this is not adequate for ADSL applications.
Another choice for improving the linearity of the line driver is to use a replica line driver to remove the error. FIG. 3 is a circuit diagram of a replica line driver to remove the error from a Class-D line driver. The signal 102 is an input to line drivers 302 and 304. Line driver 302 provides an output signal that is an input signal to a subtractor 306. The output signal of line driver 304 is an input signal to load resistance 314 and subtractor 308, which subtracts the original signal 102. The output signal of subtractor 308 is an input signal to be subtracted from the output of line driver 302 by subtractor 306. Subtractor 306 provides the output signal to load resistance 312. Load resistance 312 and load resistance 314 are also connected to ground (GND).
This circuit architecture relies on the matching of the parameters of the line drivers to cancel errors in the output. Matching of the line driver parameters is a difficult task, especially during large transient signals. Improvements on the lower frequency band are possible with this circuit architecture, but as the frequency of the input signal increases, this matching becomes less accurate. Parameters such as cross-over distortion are very difficult to cancel with this circuit architecture. Switch synchronization is also not possible for Class-D line drivers.
Another choice for improving the linearity of the line driver is to use analog adaptive filters to match the impedance characteristic of the line to the impedance of the line driver. FIG. 4 is a circuit diagram of a Class-D line driver with an analog adaptive filter 404. The signal 102 is an input to line driver 402. Line driver 402 provides an output signal that is an input signal to termination resistor 406 and to analog adaptive filter 404, both of which provide an input signal to subtractor 408, which subtracts the signal from termination resistor 406. Subtractor 408 provides a correction signal 412 to the source (not shown) that supplies the signal 102 to the line driver 402. The feedback of correction signal 412 helps to cancel the echo and distortion at the output of the line impedance 410. Line impedance 410 is connected to ground (GND).
The analog adaptive filter 404 simulates the line impedance and alleviates the distortion requirements of the line driver 402. However, implementing this analog adaptive filter 404 on an integrated circuit chip is a difficult task. The noise of this analog adaptive filter 404 needs to be low and this requires large capacitors and small resistors. Also the distortion of the analog adaptive filter 404 needs to be lower than the line driver 402. Another problem is that the time constant of the analog adaptive filter 404 needs to be low, and this also requires large capacitors that consume consider area on the chip. In the past, simple second order filters were implemented and performance gains of 10 dB were reported. Increasing the filter order is difficult and the power consumption can become too large. This type of circuit architecture is inadequate for ADSL applications.
Another choice for improving the linearity of the line driver is to use pre-distortion techniques to pre-distort the input signal by the inverse of the transfer function of the line driver, and then use this signal as the input to the line driver. FIG. 5 is a circuit diagram of a Class-D line driver with a pre-distortion circuit 502 to receive the input signal 102, which is distorted and output to the line driver 504. Line driver 504 outputs a signal 506 that is has little distortion compared to input signal 102.
A digital signal processor (DSP, not shown) constantly monitors the output of the line driver 504 and creates a table of pre-distortion functions. The data is then sent to the pre-distortion circuit 502. This is a very successful architecture and is used in high power radio-frequency transmission. However, this architecture is not suitable for a DSL system. On the transmitter side the THD is xe2x88x9260 dB and there is no need to improve this parameter. Since the transmit data rate is much higher than the receive data rate, the DSP has to work harder to remove the error for the whole transmit frequency band and not only the receive frequency band. This architecture is best suited for channels with constant impedance and not channels exhibiting transfer function nulls, because this architecture does not take into account any frequency dependence. Therefore, this architecture is only applicable to channels with narrow bandwidths (e.g., even 10 MHz of radio-frequency band on a 1 GHz carrier is considered to be a narrow band system).
Errors can be removed from the received signal by using a proper hybrid. The reduction of the error is entirely dependent on how well the impedance match of the line can be simulated by the filter. Since the line impedance varies depending on different loop characteristics, there is a limit on how much attenuation is possible. A simple hybrid attenuates echoes up to 10 dB. More elaborate hybrids can attenuate up to 24 dB.
The above description of line drivers illustrates some of the requirements of DSL and ADSL technology. What is needed is a highly efficient, low noise and low distortion line driver for driving DSL and ADSL lines. Moreover, such line drivers preferably should be relatively inexpensive (or at least not significantly more expensive than comparable existing line drivers).
The present invention provides a highly efficient, low noise and low distortion line driver for central office transmitters in ADSL applications.
The invention provides an improved line driver architecture. The invention can be implemented in numerous ways, such as a method, a system, an apparatus, and a program on electronic-readable media. Several aspects of the invention are described below.
In accordance with a first aspect of the invention, the invention provides a method to increase the power efficiency of a line driver. The method includes supplying an original input signal from a digital signal processor to a first subtractor circuit; supplying an output signal from the first subtractor circuit as an input signal to a modulator of a line driver having an output signal; providing a first closed loop path to subtract the output signal from the line driver from the original input signal of the first subtractor circuit; filtering the output signal from the line driver with a termination resistor and a low pass filter; routing the output signal from the line driver to a line impedance match filter; providing a second closed loop path including a first analog-to-digital converter and a second subtractor to subtract an output signal from the line impedance match filter from an output signal from the low pass filter; providing a third closed loop path including a digital filter and a second analog-to-digital converter; and subtracting an output signal of the digital filter from an output signal of the first analog-to-digital converter at a third subtractor circuit to output a feedback signal to the digital signal processor.
In accordance with a second aspect of the invention, the invention provides an ADSL system with a line driver. The line driver includes a first subtractor having a first input port, a second input port, and an output port producing an output signal; a digital signal processor to supply an original input signal to the first input port of the first subtractor; a Class-D line driver having an output signal on an output port and receiving an input signal to a modulator from the output signal of the first subtractor, wherein a first closed loop path is provided from said output port of the Class-D line driver to the second input port of the first subtractor; a line impedance match filter producing an output signal, receiving the output signal of the line driver as an input signal; a low pass filter having an output signal, receiving the output signal of the line driver as an input signal through a termination resistor; a second subtractor circuit to subtract the output signal from the line impedance match filter from the output signal received from the low pass filter, wherein the second subtractor provides an input signal to a first analog-to-digital converter with an input port and an output port; a second analog-to-digital converter with an input port and an output port; a digital filter with an output port and an input port to receive an input signal from the output port of the second analog-to-digital converter; and a third subtractor to subtract an output signal from the output port of the digital filter from an output signal from the output port of the first analog-to-digital converter, wherein the third subtractor outputs a feedback input signal to the digital signal processor.